1. Field of the Invention
Embodiments of the present invention relate generally to video processing and more specifically to prescient cache management methods and systems.
2. Description of the Related Art
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A graphics pipeline generally splits into three main functional stages, namely, the application stage, the geometry stage, and the rasterization stage. The application stage generates the 3D triangles that are representative of a scene. The geometry stage transforms these 3D triangles into 2D triangles and projects the 2D triangles onto a screen according to certain view points. Then the rasterization stage dices these 2D triangles into pixels and computes a color for each of these pixels to form the final image.
The rasterization stage generally includes one or more Raster OPeration (“ROP”) units, each of which is responsible for reading and writing depth and stencil data, comparing depth and stencil data, reading and writing color data, and performing alpha blending and testing. These ROP units frequently access the frame buffer, where many of the data types mentioned above are stored. The frequent accesses, however, consume significant bandwidth of the frame buffer and create bottlenecks in the graphics pipeline.
One way to improve the performance of the ROP units and, consequently, the overall performance of the graphics pipeline is to reduce the number of accesses to the frame buffer. A common approach is to use a cache to store frequently accessed data, so that the ROP units can access the cached data without having to retrieve the data from or write the data to the frame buffer. However, given the various design and cost constraints, only a limited size cache is feasible. As a result, cache misses can still occur regularly and result in significant penalties, which degrade the overall performance of the graphics pipeline.
Moreover, most caches are reactive in nature, because the decisions to either cache or evict certain in these caches are made at the time the data arrive. Without the foresight of the data that will arrive in the future, these caching decisions are necessarily imperfect.
As the foregoing illustrates, what is needed is a way to efficiently and intelligently utilize the limited caching resources to enhance the performance of the ROP units and the overall performance of the graphics pipeline.